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CAT93C76 (Rev. A)
8K-Bit Microwire Serial EEPROM FEATURES
I High speed operation: 3MHz @ VCC I Low power CMOS technology I 1.8 to 5.5 volt operation I Selectable x8 or x16 memory organization I Self-timed write cycle with auto-clear I Software write protection
H
GEN FR ALO
EE
LE
A D F R E ETM
2.5V
I Power-up inadvertant write protection I 1,000,000 Program/erase cycles I 100 year data retention I Industrial and extended temperature ranges I Sequential read I "Green" package option available
DESCRIPTION
The CAT93C76 is an 8K-bit Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC or Not Connected) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C76 is manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, SOIC, TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
FUNCTIONAL SYMBOL
SOIC Package (S, V)
VCC
CS SK DI DO
1 2 3 4
8 7 6 5
VCC NC ORG GND
ORG CS SK DI DO
TSSOP Package (U,Y)
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
GND
PIN FUNCTIONS
Pin Name CS SK Function Chip Select Serial Clock Input Serial Data Input Serial Data Output +1.8 to 5.5V Power Supply Ground Memory Organization No Connection
TDFN Package (RD4, ZD4)
CS 1 SK 2 DI 3 DO 4
8 VCC 7 NC 6 ORG 5 GND
DI DO VCC GND
Top View
ORG NC
Note: When the ORG pin is connected to VCC, x16 organization is selected. When it is connected to ground, x8 organization is selected. If the ORG pin is left unconnected, then an internal pull-up device will select x16 organization.
(c) 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice.
Doc. No. 1090, Rev. A
CAT93C76 ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55C to +125C Storage Temperature ........................ -65C to +150C Voltage on any Pin with Respect to Ground(1) ............. -2.0V to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses exceeding those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Min 1,000,000 100 2000 100 Typ Max Units Cycles/Byte Years Volts mA
D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO ILORG VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current ORG Pin Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG=GND CS=0V ORG=Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V ORG = GND or ORG = VCC 4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC 5.5V IOL = 2.1mA 4.5V VCC 5.5V IOH = -400A 1.8V VCC < 4.5V IOL = 100A 1.8V VCC < 4.5V IOH = -100A VCC - 0.2 2.4 0.1 -0.1 2 0 VCC x 0.7 Min Typ 1 300 2 0(5) 0(5) 0(5) 1 Max 3 500 10 10 10 10 10 0.8 VCC + 1 VCC x 0.2 VCC+1 0.4 Units mA A A A A A A V V V V V V V V
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. (3) These parameters are tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1V to VCC +1V. (5) 0 A is defined as less than 900 nA.
Doc. No. 1090, Rev. A
2
CAT93C76
PIN CAPACITANCE Symbol COUT
(1)
Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG)
Conditions VOUT=0V VIN=0V
Min
Typ
Max 5 5
Units pF pF
CIN(1)
INSTRUCTION SET(2) Address Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Bit 1 1 1 1 1 1 1 Opcode 10 11 01 00 00 00 00 x8 A10-A0 A10-A0 A10-A0 x16 A9-A0 A9-A0 A9-A0 D7-D0 x8 Data x16 Comments Read Address AN- A0 Clear Address AN- A0 D15-D0 Write Address AN- A0 Write Enable Write Disable Clear All Addresses D7-D0 D15-D0 Write All Addresses
11XXXXXXXXX 11XXXXXXXX 00XXXXXXXXX 00XXXXXXXX 10XXXXXXXXX 10XXXXXXXX 01XXXXXXXXX 01XXXXXXXX
A.C. CHARACTERISTICS Limits VCC = 1.8V-2.5V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 200 250 250 250 1000 DC CL = 100pF (3) Test Conditions Min 100 0 100 100 250 250 150 5 150 150 150 100 3000 Max VCC = 2.5V-5.5V Min 50 0 50 50 150 150 100 5 Max Units ns ns ns ns ns ns ns ms ns ns ns ns kHz
NOTE: (1) These parameters are tested initially and after a design or process change that affects the parameter. (2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are "don't care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands. (3) The input levels and timing reference points are shown in the "AC Test Conditions" table.
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Doc. No. 1090, Rev. A
CAT93C76
POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages
50ns 0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC
4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC 4.5V 1.8V VCC 4.5V
NOTE: (1) These parameters are tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
DEVICE OPERATION
The CAT93C76 is a 8192-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C76 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13-bit instructions control the read, write and erase operations of the device. When organized as X8, seven 14-bit instructions control the read, write and erase operations of the device. The CAT93C76 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). The most significant bit of the address is "don't care" but it must be present.
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Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C76 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C76, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a memory location before it is written into.
Doc. No. 1090, Rev. A
CAT93C76
Figure 1. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure 2. Read Instruction Timing
SK
CS Don't Care AN DI 1 1 0 AN-1 A0
DO
HIGH-Z
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D 7 . . . D0
Address + 2 D15 . . . D0 or D 7 . . . D0
Address + n D15 . . . or D7 . . .
Figure 3. Write Instruction Timing
SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY
5
Doc. No. 1090, Rev. A
CAT93C76
Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state. Erase/Write Enable and Disable The CAT93C76 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C76 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C76 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the self-timed high voltage cycle. This is important because if CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Power-On Reset (POR) The CAT93C76 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3 V.
Figure 4. Erase Instruction Timing
SK
CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0
STATUS VERIFY tCS
STANDBY
tHZ BUSY tEW READY HIGH-Z
Doc. No. 1090, Rev. A
6
CAT93C76
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE=11 DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
1
0 tSV tHZ BUSY tEW READY HIGH-Z
DO
HIGH-Z
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCSMIN
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
7
Doc. No. 1090, Rev. A
CAT93C76 ORDERING INFORMATION
Prefix CAT Optional Company ID Device # 93C76 S Suffix I Temperature Range I = Industrial (-40C to +85C) E = Extended (-40C to +125C) TE13 Rev A
(2)
Product Number
Tape & Reel
Die Revision Package P = PDIP S = SOIC (JEDEC) U = TSSOP RD4 = TDFN (3x3mm) L = PDIP (Lead free, Halogen free) V = SOIC, JEDEC (Lead free, Halogen free) Y = TSSOP (Lead free, Halogen free) ZD4 = TDFN (3x3mm, Lead free, Halogen free)
Notes: (1) The device used in the above example is a 93C76SI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA.) For additional information, please contact your Catalyst sales office.
Doc. No. 1090, Rev. A
8
CAT93C76 REVISION HISTORY
Date 08/11/04 Revision Comments A Initial Issue
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Doc. No. 1090, Rev. A
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DPP TM AE2 TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
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Publication #: Revison: Issue date:
1090 A 08/11/04

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